IEEE Ottawa Section
Video Course on Microelectronic Failure Analysis
Last updated 15 Sept 2000 -

During the Fall Semester of 1997, thirty 75-minute lectures in Microelectronic Failure Analysis were given at the University of New Mexico (UNM) and transmitted via satellite to manufacturing sites across the USA; it is now available on videotape through the IEEE. The course was designed and delivered by experienced, recognized persons who are leaders in failure analysis practice, development, and conference leadership. This produces a depth and breadth of coverage that a single person could not do. Experts from industry conceived the course not only to fill a void in university teaching of failure analysis but also to allow strong participation. These lectures were a part of a graduate course: a joint venture of the UNM, Sandia National Labs, and the Product Analysis Forum (PAF) of Sematech. Many of the listed speakers also give tutorials at the ATM-sponsored ISTFA (International Symposium for Testing and Failure Analysis); this is the pre-eminent annual conference for microelectronics failure analysis.

Managers and practicing engineers within failure analysis departments will benefit greatly from this extensive course. Viewers should have a basic knowledge of transistor devices (MOSFET) and IC technology. A background in IC manufacturing is helpful, but not essential. This set consists of all thirty lectures on videotape, presentation notes. The textbook is Microelectronic Faiure Analysis Desk Reference, 3rd Edition (ASM International, 1993) - 450pp; about $150US. The 4th Edition is now available - the "course copy will be available for inspection at some of the sessions.

• Technical Foundations of Failure Analysis
• Etching: wet, dry, Focused Ion Beam analysis
• Imaging: optical, e-beam, Transmission Electron Microscopy, Electron- & Optical-Beam Induced Current thermal, & backside measurement
• Recent Techniques: Charge Induced Voltage Alteration, RCI, leakage currents - IDDt
• Management and Business of Failure Analysis

From this video you will learn

• The technical foundations of failure analysis: test, reliability, design impact, packaging, and fabrication
• Selection of etch and delayering techniques
• How to select one of the many imaging techniques
• New techniques, used by leading edge companies, for analysis of deep submicron ICs having up to seven layers of metal

Information above is derived from text found at   http://www.ieee.org/organizations/eab/circuitdev/circuit12.htm
See the biographical notes for the presenters   Fee structure

Full course details - All courses A thru H are 9 am - noon;
subsequent showings are mornings, at the times stated. There are no plans to re-run most of the series..

A - Introduction & Management Issues - Wed 22 March 2000 - 9 am - noon - registration from 8.30 am - Communications Research Centre - Building 2 Auditorium

• Introduction: Course Mechanics, Course Overview, etc.; overview of how FA is a critical part of the IC industry; business value of FA; relationship of FA to design, test, process, Q&R, etc. - Ted Dellin 01 € 42 slides 21 pages
• The Failure Analysis Process: decision-making aspects, etc. - Dave Vallett 02 € 34 slides 17 pages

B - Business Perspectives of Failure Analysis - Wed 29 March
9 am - noon - Communications Research Centre

• Overview of FA Process in Industry: big picture, business perspective, where does FA fit in company, cost, economics - Sudhakar Kudva 30 € 24 slides 12 pages
• Business aspects of FA: lab models, cost of ownership, etc. - Dick Ross 28 € 89 slides 45 pages

C - Design, Fabrication and Failure Modes of CMOS ICs - Wed 5 April,
Carleton U, ME4124 - McKenzie Engineering Building

• CMOS IC fabrication: fab (etch, photolithography, implantation, etc.) and physical (layout, etc.) aspects. Steve Hersee 03 € 39 slides 20 pages 
• CMOS IC electrical testing: testing, characterization, and diagnosis; test approaches including functional, stuck-at, scan, Built-in Sytem Test, delay, IDDQ, etc.- Ken Butler 04 € 43 slides 22 pages

D - Reliability of CMOS ICs and Designing for Failure Analysis - Friday 7 April,
Carleton U, ME4124 - McKenzie Engineering Building

• CMOS IC Design: design and electrical aspects; design for diagnosis and FA. - Doug Josephson 05 € 39 slides 20 pages 
• CMOS IC Quality and Reliability: sources of failure yield, reliability, field, etc.;  why FA approach depends on source - Steve Hersee and Chuck Hawkins 06 € 65 slides 33 pages (with #7)

E - Failure Modes of Silicon ICs - 1 - Wed 12 April,
Carleton U, ME4124 - McKenzie Engineering Building

• Electrical Failure Modes and Models: electrical behavior of dominant CMOS defects and failure mechanisms and relationship to common models.- Chuck Hawkins 07 € slides part of 6/7 package
• Physical failure modes and mechanisms: dominant types (oxide breakdown, bridging shorts, interconnect opens, EM). - Bill Miller 08 - copying in process

F - Failure Modes of Silicon ICs - 2 - Friday 14 April,
Carleton U, ME4124 - MacKenzie Engineering Building

• Electrical Over-Stress and Electrostatic Discharge Failures - Ian Morgan 27 € 49 slides 25 pages 
• MEMS: Microelectromechanical Systems: Reliability and Failure Analysis - Danelle Tanner and Ken Peterson  25 

G - Packaging & Depackaging and Deprocessing of ICs - Wed 26 April, 9 am
Carleton U, ME4124 - MacKenzie Engineering Building

• Package analysis and depackaging: plastic/ceramic, DIP, PGA, PQFP, surface mount, etc., + RGA and related issues; jet-etching; acoustic and x-ray radiography techniques, etc. - Dave Palmer 09 - copying in process 
• Deprocessing: nitride/oxide passivation, metal/oxide layer removal, wet/dry processes, X sections, surface/parallel polishing, etc. - Mike Strizich 10 - copying in process

H - Optical and Electron Beam Inspection Techniques - Friday 28 April, 9 am - Chipworks - 3685 Richmond Rd, Bells Corners - directions

• Inspection: Optical techniques: basic optics plus IR, Nomarski, SOM, etc. - Larry Wagner 11 
• Inspection: SEM techniques: surface interaction physics, SE surface topography, backscatter, PVC, + basic VC.- Larry Wagner 12

I - Techniques for Electrical and Physical Analysis of Circuit Die - Wed 3 May, 9 am, Mitel Kanata - directions

• Internal die electrical testing: mechanical probing for DC parametrics (Vt, etc.) and basic e-beam testing.- Bob Rao 13
• Physical/surface analytical techniques: Auger, TEM, SIMS. - Charles Barbour 14

J - Techniques for Defect Localization - 1 - Fri 5 May, 9 am,
Chipworks, Bells Corners

• Localization: Light (photon) emission: basics, commercial systems, spectral signatures, Near -IR, etc. - Gary Shade 15 
• Thermal Localization: liquid crystal, IR, FMI, etc - Dan Barton 16

K - "Micro" Processing for Circuit Analysis - Wed 10 May, 9 am,
Mitel Kanata - directions

• Focused ion beam systems: precision cross sections, device mods, VC, probe points deposition, etc. - Ann Campbell 17
• Dry etch - Loren Hahn 18 € 26 slides 13 pages

L - Reverse Engineering of CMOS ICs - Fri 12 May, 9 am,
Mitel Kanata - directions

• Construction Analysis and Reverse Engineering - Mark Masters 19
• Customer Perspective - some comments - Gerald Servais 20

M - Techniques for Defect Localization - 2 - Wed 17 May, 9 am - 2pm, 45 minute lunch break - Communications Research Centre, Bldg 74 conference room (room 223) - directions

• Scanning Probe Microscope localization: basic, MFM/CCI, electro-optic, etc.- Pai Tangyungyong 21 
• SEM & Electron Beam: EBIC, RCI, CIVA, LECIVA, etc. - Ed Cole 22
• Optical Probe Techniques: Scanning Optical Microscope: OBIC, LIVA, etc. - Ed Cole 23

N - Management and Future Challenges for Failure Analysis - Fri 19 May, 9 am - 2pm, 45 minute lunch break - Auditorium, Communications Research Centre - directions

• Failure Analysis Information Management: knowledge-based FA, expert systems, signature analysis, paperless labs, reports, etc. - Chris Henderson 24 
• A Specific Case History: walk through the process, emphasis on decision-making, perspective, intelligence - Steve Ferrier 26
• FA & Diagnosis Future: needs, challenges, design for FA, etc. - interactive, using a challenge or two and have students brainstorm approaches or solutions.- Larry Wagner 29 - copying in process

  1998 / 37 Hrs. 30 Min. / 30 Video Tapes List Price US$5000.00 NTSC Order No. HV7024-QIA, NTSC ISBN 0-7803-4585-1 

The proposed structure above has been produced by Julian Noad and Hugh Reekie.
Note -  the suffix number, e.g. 08, above, are IEEE lecture sequence numbers; the notes are in this order.

The Mackenzie Engineering Building, Carleton University is at the corner of Library Road and Campus Ave. It is west of the railroad that runs through campus. The Minto Centre is attached to it. The Minto Centre has dark brick and there is a round 150'Diam lecture theater as part of the Centre. Parking (not cheap) is in the visitors lot just south of the MacKenzie building on Campus Ave. Parking arrangements changed in early 2000. 4124, Mackenzie Building. The building has 5 blocks, connected by stairwells. From outside find the block with a full 4th floor.This block is the one to the South east - i.e. nearest the parking lot. If you enter the right block, the room numbers will be 2100 to 2199. The 3th floor is numbered like it was the 4th, i.e. 4100 to 4199. - courtesy Cal Plett

Mitel, Kanata - 360 Leggett Drive (near Canadian Marconi) - Please park across the road from the Mitel main entrance (lots of space). You will be met at the Mitel main entrance. A detailed map is available - at previous sessions. courtesy Judy Horner.

Communications Research Centre Complex, Shirley Bay- 3701 Carling Ave, west of Moodie and Range Road (to Shirley Bay) just before the railroad overpass, take signed road to right at traffic lights. Sign in at gatehouse and enquire about parking ( a long walk). You will be escorted to Bldg 2 Auditorium; or there may be a longer walk to another location - specified at the guardhouse - Courtesy Friends of CRC and Tom Carroll.

Chipworks, 3685 Richmond Road ( previously a Computing Devices building). Opposite Best Western Motel, see signs to Nortel and Chipworks. Follow signs, park and proceed to main entrance. The conference room is close by. Courtesy Ray Haythornthwaite.

Nortel Semiconductor - 185 Corkstown, near Moodie Drive, just n of Queensway. Probably the MacKenzie Conference Room, main or south door. Register and you will be escorted. Courtesy Ian Few.

• $300 per person - quantity, advanced registration - 5 persons or more per company - submitted together
• $350 - regular advanced registration - individual rate (less $100 if IEE/IEEE member)
• $100 - late registration surcharge after Fri 17 March - but only $50 student surcharge
• No charge for the re-runs, for previous registrants who missed for any reason.
• $150 - pre-registration, full time students (less $50 if IEE/IEEE student member)
  • fees are higher than planned - course notes have 300+ more pages than expected
  • The fees include course notes in binders - about 900 pages - includes selected published papers
  • CRC (& Friends) may attend CRC sessions at no charge, but pay for course notes if needed
  • Carleton U location, and West-end locations to be finalized with adequate notice
  • Single session registration permitted - course notes require advanced notice
  • Personnel substitutions permitted (not for IEEE/IEE registration discount);
  • 20% discount for questionnaire respondents

  To register pse fill in the form, advise course co-ordinator by email, and mail in your fee.

Ted Dellin - Program Manager of Reliability Programs at Sandia National Labs. This includes program management of the Electronics Quality/Reliability Center, which works with many semiconductor manufacturers and vendors in reliability and failure analysis. He has orgnized the development of the 1997 Sematech Reliability Roadmap and participated in the 1997 SIA National Technology Roadmap for Semiconductors.
David P. Vallett - The 1997 chair of the SEMATECH Product Analysis Forum. He joined IBM in Burlington, VT in 1982 as a CMOS product characterization engineer and in the past six years has sened as manager and team leader of failure analysis technology development. His professional interests are in fault localization techniques and the impact of technology scaling on failure analysis.
Steve D. Hersee. A Professor in the EECE department of the University of New Mexico; has taught microelectronics processing since 1992. He has worked for major semiconductor corporations in Europe and the USA for 22 years prior to joining the university.
Kenneth M. Butler - A Senior Member of the Technical Staff of Texas Instruments in the ASIC Software Engineering Senices Division. He works with design groups in TI's Semiconductor Group in design for testability, automatic test pattern generation, automated failure diagnosis, and automated tester program generation. He has taught test tutorials inside TI and externally for ISTFA.
Doug Josephson - A high speed microprocessor designer with Hewlett Packard's Systems Technology Division in Fort Collins, Colorado.  Team leader for the design, test, and characterization of five HP PA-RISC microprocessors used in Hewlett Packard servers and workstations.
Charles F. Hawkins - A Professor in the EECE Dept. at the University of New Mexico. His research has been in testability, defect based testing, reliability, and failure analysis. He was General Chair of International Test Conference in 1996 and Program Chair in 1993; he co - authored several Conference Best Paper Awards in CMOS IC test. He also teaches short courses for industry in design, test, and reliability.
Bill Miller - Manager of the Sandia Labs Reliability Physics Dept. He performs fundamental research in metals, oxides and MEMS. Many contributions to oxide wearout understanding.
Dave Palmer - Manager of the IC Packaging Group at Sandia Labs. He has taught several courses at UNM and is active in the Components, Packaging, Manufacturing Technology Society of the IEEE.
Michael P. Strizich - President of Analytical Solutions in Albuquerque, NM; peforms device analysis, including in-depth electrical characterization, reverse engineering, process evaluation, and failure analysis of complex semiconductor devices. Mike started his career in the Failure Analysis Group at National Semiconductor in Santa Clara, CA.
Larry Wagner - Member of Texas Instruments staff - with diverse and depth experience in failure analysis and teaching in-house courses on this subject. He was General Chairman of ISTFA in 1995 and is a member of the Sematech Product Activities Forum (PAF) . He is writing a book on failure analysis.
Bob Rao - Member of the Intel Technical Staff - with pioneer experience with e-beam technology at Cambridge University, particularly with respect to lithography applications. He serves on several ISTFA committees.
Charles Barbour - Senior member of the Sandia Labs technical staff - specializes in Surface Chemistry. He has co-authored 2 books, has published widely, and has given several university lectures on these subjects.
Gary Shade - Manager, Failure Analysis Dept., Ford Microelectronics, Colorado Springs, Colorado. The 1994 General Chair of the International Symposium on Test and Failure Analysis (ISTFA). He has diverse skills in failure analysis and in depth knowledge of light emission phenomena in IC defects.
Dan Barton He is a senior member of the Sandia Labs technical staff in the Failure Analysis Dept. - works in Fluorescent MicroThermal Imaging. He was a winner of an R&D 100 award.
Ann Campbell - 1998 General Chair of the Reliability Physics Symposium. She is a Senior Staff Member of the Sandia Labs Failure Analysis Dept. Her interests lie in development of focus ion beam applications for IC failure analysis.
Loren Hahn - Member of IBM Failure Analysis Dept. in Essex Junction, Vermont. He specializes in e-beam applications.
Mark Masters - Member of IBM Failure Analysis Dept. in Essex Junction, Vermont. He has diverse failure analysis skills and specializes in construction analysis and reverse engineering.
Gerald E. Servais - Staff Research Engineer, Delco Electronics - Supervisor of Digital Parts Engineering Group and for the last 6 years supervisor of the Parts Research & Test Development Group at Delco. One of founders of the CDF Automotive Electronics Council - developing automotive standards for the qualification of integrated circuits, discrete semiconductor devices, and passive components.
Pai Tangyunyong - Senior member of the Sandia Labs technical staff - works with atomic force microscopy and Fluorescent MicroThermal Imaging.
Ed Cole - The 1996 General Chair of the International Symposium on Test and Failure Analysis (ISTFA). He works with the Sandia National Labs Failure Analysis Dept. He has won several conference Best Paper awards and is the recipient of an R&D 100 Award in 1995. He is the developer of the CIVA, LECIVA, and LIVA FA techniques.
Chris Henderson - Senior member of the Sandia Labs technical staff, Failure Analysis Dept. - works with applying expert system technology to failure analysis. He was a wimner of an R&D 100 award.
Danelle Tanner - Senior member of the Sandia Labs technical staff - works with MEMS reliability model development. She has also worked in IC oxide wearout failure mechanisms.
Ken Peterson - A senior member of the Sandia Labs technical staff - he works in MEMS and MCM failure analysis.
Steve Ferrier - A senior member of the Hewlett Packard Failure Analysis Dept., Corvallis, Oregon. In 1997, he won an Outstanding Paper Award at ISTFA for his work on thermal modeling.
Ian Morgan - Member of the AMD Corp. Technical Staff - specializing in EOS/ESD. HE has taught many inhouse courses for AMD on these subjects and especially how failure analysis is linked to root cause determination.
Dick Ross - Manager of the IBM Failure Analysis Dept. in Essex Junction, Vermont - sponsor of the Sematech Product Activities Forum (PAF). He is frequently sought as a panelist and industry representative for failure analysis concerns.
Sudhakar Kudva - A Q&R Manager at Intel in Folsum, California. He was the first Chairman of the Sematech Product Analysis forum (PAF) that was begun to stimulate R&D initiatives in failure analysis.